1. Field of the Invention
The present invention relates to an integrated circuit apparatus and a method for designing the same and, particularly, to an integrated circuit apparatus which changes the source voltage of MOSFET and a method for designing the same.
2. Description of Related Art
Recently, small semiconductor integrated circuit apparatus such as metal-oxide-semiconductor large-scale integrated circuits (MOSLSIs) have been developed, and semiconductor integrated circuit apparatus fabricated with 90 nm process technology have come into practical use. In addition to miniaturization, higher speed operation and lower power consumption are required for semiconductor integrated circuit apparatus.
While power supply voltage is reduced for lower power consumption to achieve miniaturization of MOSLSI, increase in integration density and access speed causes higher power consumption. Conventional LSIs are designed so that standby current/voltage is lower than active current/voltage in order to save power consumption. However, as the size reduction progresses, not only the active current/voltage but also the standby current/voltage has become critical. This is mainly due to increase in subthreshold leakage current and leakage current caused by reduction in insulating film thickness for miniaturization, which occurs because the operating voltage of MOSFET (which is referred to also as a MOS transistor) is reduced to about 1V for miniaturization and the threshold voltage of the MOS transistor is further reduced to about 0.2V for higher-speed operation.
As technology for reducing standby current, Multithreshold-Voltage CMOS (MTCMOS) and Variable Threshold-Voltage CMOS (VTCMOS) in normal logic circuits are known, as described in Shin'ichiro Mutoh et al., 1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 30, No. 8, August 1995 pp. 847-854, and in Tadahiro Kuroda et al., A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 31, No. 11, November 1996, pp. 1770-1779. The MTCMOS technology taught by Mutoh et al. places a MOS transistor between virtual power supplies and switches the source voltage of the MOS transistor between active and standby. Changing the source voltage in the standby state allows reduction in leakage current. The VTCMOS technology taught by Kuroda et al. also switches the source voltage effectively by changing substrate potential.
Further, technology which controls the source voltage of a MOS transistor just like the MTCMOS technology is described in Japanese Unexamined Patent Publication No. 07-86916 (Takayuki Kawahara et al.). This technology controls the source voltage by placing a parallel circuit of “resistor” and “switch” between the source and a reference voltage line (substrate potential of MOSFET). The “resistor” turns on a given MOSFET and the “switch” turns on/off the MOSFET. Kawahara et al. also teaches a mechanism for reducing leakage current when changing the source voltage from reference voltage (substrate potential or well potential).
Examples of reducing standby current of a memory cell, not a normal logic circuit, are described in Kenichi Osada et al., 16.7-fA/Cell Tunnel-Leakage-Suppressed 16-Mb SRAM for Handling Cosmic-Ray-Induced Multierrors, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 38, No. 11, November 2003, pp. 1952-1957, and Masanao Yamaoka et al., A 300 MHz 25 μA/Mb Leakage On-Chip SRAM Module Featuring Process-Variation Immunity and Low-Leakage-Active Mode for Mobile-Phone Application Processor, IEEE International Solid-State Circuits Conference, 542, 2004, pp. 494-495. Osada et al. and Yamaoka et al. teach technology which reduces standby current of SRAM by making the source voltage of a memory cell driver transistor slightly higher than GND potential and reducing the bit line voltage of a transfer transistor. Osada et al. show leakage current components such as gate tunnel leakage current, gate-induced drain leakage (GIDL) current, and subthreshold leakage current, and leakage current at normal temperature (25° C.) and high temperature (90° C.), and describes that the leakage current significantly increases at high temperature. Osada et al. also describe the configuration which controls the source voltage of each SRAM cell. Yamaoka et al. reduce the current of entire SRAM by controlling the source voltage of an NMOS transistor.
The standby current of MOSLSI typically increases at high temperature due to temperature dependence of the subthreshold characteristics of MOSFET. In order to satisfy the required specification of products, maximum leakage current, which is presently at high temperature, should satisfy the specification. Though Osada et al. schematically show standby current at normal temperature and high temperature, they describe nothing about device temperature and temperature dependence of a circuit (FIG. 9) which controls the source voltage of a MOS transistor constituting a memory cell.
As a way of preventing standby voltage from increasing significantly at high temperature, a technique for reducing power supply voltage at high temperature is described in Japanese Unexamined Patent Publication No. 06-314491 (Hiroshi Sato). However, nothing is disclosed about the relationship between specific source voltage and temperature.
A technique which controls a refresh time (timer period) of a DRAM cell according to temperature is described in Japanese Unexamined Patent Publication No. 2003-100074 (Koichi Mizugaki). This technique keeps the same refresh time (timer period) as at normal temperature up to a given temperature and reduces the refresh time (timer period) after exceeding the given temperature with a plurality of temperature detection circuits and control circuits by using the temperature characteristics of PN junction. This technique reduces power consumption by changing the refresh time (timer period), which has been set to satisfy the refresh characteristics at high temperature in conventional techniques, according to temperature.
Osada et al. reduce standby current by making the source voltage of a memory cell driver transistor 0.5V higher than GND potential (substrate potential of MOS transistor) However, this technique always takes time to set the source voltage from boost state by 0.5V back to GND level when shifting from standby state to active state. Osada et al. actually describe that several ns of delay occurs as shown in FIG. 10. Each of the above-mentioned conventional techniques for controlling the source voltage switches the source voltage between given binary voltage values.
Setting the source voltage of a MOS transistor to be higher (or lower in the case of a PMOS transistor) than substrate potential requires reduction in ON-current. It is therefore necessary to set the source voltage to be the same as the substrate potential during active operation and particularly in high-speed operation. This has a problem that, if a difference between the source voltage and the substrate potential is large, it requires large energy and takes a longer time to set the source voltage back to the same level as the substrate potential, causing operation (access) delay to occur.